I'm a PhD student in the EECS Department at UC Berkeley. I work with Prof. Jaijeet Roychowdhury, and my research is focused on developing new algorithms and computational techniques for chip-design.
At the moment, I'm working on a project (dubbed ABCD) where the goal is to automatically derive Boolean abstractions (i.e., discrete-time, discrete-valued models such as Finite State Machines) that approximate the behaviour of continuous systems (e.g., cutting-edge analog/mixed-signal designs). The hope is that these Boolean models will be amenable to analysis using existing tools available for formal verification and model checking, which may help in proving the correctness and performance aspects of the underlying continuous systems. Also, the Boolean models so generated can be simulated very efficiently, i.e., orders of magnitude faster than traditional SPICE. For example, here is a paper that we recently published on this idea.
Before ABCD, I was working on non-stationary noise analysis. Specifically, I was building CAD tools (dubbed SAMURAI and MUSTARD) to help predict the impact of Random Telegraph Noise (RTN) on deep sub-micron SRAM and DRAM designs. Here's a talk that I gave recently at Purdue University on this topic.